Tag : Power tools
Si2 Releases Common Power Format Version 1.1

Released : Saturday, September 27, 2008 12:49 AM
The Silicon Integration Initiative (Si2) announced release of theCommon Power Format (CPF) Version 1.1, incorporating majorenhancements to the widely adopted low-power intent format.
CPF 1.1 was approved by the Low Power Coalition (LPC).
Ameesh Desai, Si2 Board Chair and Senior Director of Design Toolsand Methodology at LSI, said, "I am pleased with the rapid progressof the CPF. Efficient power utilization has become a primary needfor electronic products worldwide. The efforts by Si2's LPCcoalition members are enabling the industry to implement low-powersemiconductors that reduce costs and risks and development times."
The CPF standard reduces this risk by extending the industry'sRTL-GDSII design infrastructure to support low power designtechniques in a safe and efficient manner. In a little over a yearthe LPC has taken the next step to broaden the applicability to aneven larger set of designs and methodologies with CPF 1.1.
CPF is a Tcl-based format used to capture the power intent of adesign. CPF complements the RTL and/or netlist description of thedesign allowing existing golden RTL blocks to be used withoutmodification. CPF has achieved wide acceptance in EDA tools inend-user tool flows, and enjoys a record of numerous completed chiptape-outs with subsequent testimonials, and adoption into foundryreference flows.
The extensions in CPF 1.1 further expand support for bottom-up andtop-down hierarchical flows and enable the integration, reuse andverification of internal and 3rd party developed power aware IP.Power intent for multiple IP blocks from multiple sources can beintegrated together with appropriate resolution of power domains,power modes and power related rules. In addition, CPF 1.1 supportsmacro modeling of hard IP such as embedded memories with complexpower structures. This enables implementation and verification ofthe IP's power behaviors in the design context.
Gill Watt, CAD Manager at AMD, and chair of the LPC, said, "The LPCmembers recognize that the marketplace is demanding more powerefficient designs for both mobile and wired products. CPF 1.1contains major enhancements to extend its applicability to newdesign styles and methodologies. These enhancements provide greaterflexibility particularly for designs that re-use IP from multiplesources. This flexibility is expected to expand the use ofpower-aware techniques from specialized power-critical designs intowidespread practices used in all mainstream designs, allowing LPCmember companies to provide more power efficient products to themarketplace."
The Low-Power Coalition (LPC) is delivering enhanced capabilitiesin low-power Integrated Circuit (IC) design flows in particularrelating to specifications of low-power design intent,architectural tradeoffs, logical/physical implementation, designverification and testability. Member companies are: Advanced MicroDevices, ARM, Atrenta, Azuro, Cadence Design Systems, CalyptoDesign Systems, ChipVision Design Systems, Entasys, Envis,Freescale Semiconductor, Global Unichip, IBM, Intel, LSI, NXPSemiconductors, Sequence Design, and Virage Logic. The Low PowerCoalition is an open industry group operating under the auspices ofSi2.
Si2 is an organization of semiconductor, systems, EDA, andmanufacturing companies focused on improving the way integratedcircuits are designed and manufactured in order to speed time tomarket, reduce costs, and meet the challenges of sub-micron design.
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(Distributed on behalf of 10Meters via M2 Communications Ltd -http://www.m2.com) (10Meters - http://www.10meters.com)
Copyright 2008 Wireless News
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